The present invention relates to self-aligned processing of a semiconductor device, and more particularly, but not exclusively relates to a technique to provide a self-aligned etch stop layer.
The advance of Integrated Circuit (IC) technology toward high density, high performance integration is achieved not only by decreasing feature size, but also by an increased tolerance to misalignments relative to the features. Such misalignments usually occur during later processing phases of semiconductor device fabrication. This tolerance arises in some instances because the semiconductor features, such as transistor gates, are becoming so small that standard lithographic technology is incapable of repeatedly defining structures relative to the gate without some variation in location. The resulting misalignments typically occur when metal contacts to a transistor are being lithographically defined.
In order to manage such misalignments, specially defined etch stops are sometimes utilized. Unfortunately, these approaches often require the placement of an etch stop layer on transistor gates during initial patterning. This approach precludes the ability to perform other processes to the gate without extensively complicating the overall fabrication process. For example, the placement of a nitride etch stop on the transistor gate during initial processing prevents self-aligned silicidation of the gate in later stages. Also, p+ and n+ gate implantation common to CMOS processing cannot be performed once the etch stop is in place. Moreover, adding the etch stop in a later stage with a dedicated mask and lithographic procedure would suffer from the same misalignment problems as contact placement.
Thus, there is a need for a technique to provide a gate etch-stop without resorting to a mask or lithographic procedure. The present invention meets this need and provides other important advantages.
The present invention relates to self-aligned processing of semiconductor devices. Various aspects of the invention are novel, non-obvious, and provide various advantages. While the actual nature of the invention covered herein may only be determined with reference to the claims appended hereto, certain aspects which are characteristic of the preferred embodiments disclosed herein are described briefly as follows.
One aspect of the present invention is a self-aligned etch stop to increase process tolerance to misaligned semiconductor contacts.
In another aspect, a self-aligned gate etch-stop is provided by coating a semiconductor device that defines a field effect transistor structure. The structure has a source contact region and a drain contact region with a gate positioned therebetween. A portion of the coating is removed to define a generally planar surface along the coating and expose a portion of the gate. The exposed gate may have a surface generally coplanar with the coating surface by virtue of this removal stage. A recess is formed in the surface by removing a portion of the gate material. An etch stop barrier is deposited, at least partially filling the recess and contacting the surface. A portion of the barrier is removed, reexposing the coating, but leaving the recess at least partially filled with the barrier.
In still another aspect, a self-aligned gate etch-stop is provided by coating a semiconductor device that defines a field effect transistor structure. The structure has a source contact region and a drain contact region with a gate positioned therebetween. A portion of the coating is removed by chemical-mechanical polishing to expose a portion of the gate. A recess is formed in the exposed the gate by removing at least a portion of the gate material. An etch stop barrier is deposited, at least partially filling the recess and contacting the surface. A portion of the barrier is removed, reexposing the coating, but leaving the recess at least partially filled with the barrier. The barrier may also be removed by an appropriate chemical-mechanical polishing technique.
An additional aspect of the present invention is a process for manufacturing an integrated circuit that includes defining a region of a silicon substrate for formation of a field effect transistor. The region is bounded by a field isolation structure and includes a source, a drain, and a gate positioned between the source and drain. The gate includes a gate oxide pad formed on the substrate and a polysilicon gate member formed on the gate oxide pad. The polysilicon member has a thickness extending above the source and drain and is bounded by a pair of spacer walls. During the process, the source, the drain, the gate, and the spacer walls are covered with a silicon nitride liner and a silicon dioxide layer is deposited on the silicon nitride liner. At least a portion of the silicon nitride liner and the silicon dioxide layer have a combined thickness greater than the thickness of the polysilicon member. This process includes removing a portion of the silicon dioxide layer by chemical mechanical polishing to expose the polysilicon member without exposing the source or drain to thereby define a first generally planar surface; and etching the exposed polysilicon member to controllably form a recess relative to the first generally planar surface. A self-aligned silicidation process is performed to form a silicide layer in the recess. Alternatively, a chemical vapor deposition of a metal, such as tungsten, may be employed to partially fill the recess. A silicon nitride layer is provided that fills the recess and covers the first generally planar surface. A part of the silicon nitride layer is removed to reexpose the silicon dioxide layer and leave a portion of the silicon nitride layer in the recess on top of the silicide layer. The formation of the field effect transistor is then completed.
In a further aspect of the present invention, a number of semiconductor device features are formed that extend from a semiconductor substrate. These features are spaced apart from each other to define a corresponding number of gaps therebetween. The features and the substrate are coated. The resulting coating occupies at least a portion of each of the gaps. A portion of the coating farthest away from the substrate is removed by chemical-mechanical polishing to expose each of the features. A self-aligned process is performed with the features exposed by the removal. The features may be transistor gates.
An additional aspect of the present invention includes: (a) forming a semiconductor device feature that extends from a semiconductor substrate; (b) covering the feature and the substrate with a coating; (c) removing a part of the coating farthest away from the substrate to form a generally planar region along the coating and expose the feature; and (d) performing a self-aligned process to the exposed feature. The removal of coating may include the removal of part of the feature to define a feature surface and a coating surface that are generally coplanar. Also, the feature may include a polysilicon member of a field effect transistor gate.
Accordingly, it is one object of the present invention to provide a self-aligned technique for modifying features of a semiconductor device. This technique may include providing a self-aligned gate etch stop.
It is another object of the present invention to perform a self-aligned process to modify a transistor gate so that misalignment of transistor contacts may be better tolerated.
It is still another object of the present invention to define a recess in a polysilicon gate member for filling by an etch stop material such as silicon nitride.
Further objects, features, benefits, aspects, and advantages of the present invention shall become apparent from the detailed drawings and descriptions provided herein.